As device geometry is scaled down to deep submicron region, the parasitic capacitance between closely spaced metal lines becomes important in terms of the resistance-capacitance time delay for device switching [M. T. Bohr, in Tech. Dig. IEEE Int. Electron Devices Meet., 241 (1995)]. A novel interlevel dielectric (ILD) with a low dielectric constant (k) is thus required to reduce the parasitic capacitance. Spin-on coated methylsilsesquioxane (MSQ) is very promising as a novel ILD, due to its low k value (.about.2.8) and superior thermal stability (.about.500.degree. C.). However, the MSQ film can be degraded in the resist ashing step after damascene trenches of the film are patterned using dry etching [J. Waeterloos, H. Meynen, B. Coenegrachts, S. Vanhaelemeersch, J. Grillaert, and L. Van den hove, in Advanced Metallization and Interconnect Systems for ULSI Applications in 1995, R. C. Ellwanger and S. Q. Wang, Editors, p.75 (1996); J. J. Yang, S. Q. Wang, L. Forester, and M. Ross, in Advanced Metallization for ULSI Application in 1997, R. Cheung, J. Klein, K. Tsubouchi, M. Marakami, and N. Kobayashi, Editors, p. 359 (1997)]. The degraded MSQ film can easily become hygroscopic, and seriously lose its benefit of having low k. Therefore, ashing-induced degradation becomes an important issue in terms of applying MSQ film as an option for damascene integration.
A primary object of the present invention is to provide a method to improve the drawback of the prior art.